If you connect the inout to an intermediate signal, you should be able to connect it to the input
BUT you need a tri-state buffer connected to the inout port, otherwise the design wont compile.
What is the major use of having a tristate buffer inside FPGA?. Only it is necessary when you interface with external devices, not internal FFs.Correct me if wrong
You only need to drive 'z' when opposite end drives its enable signal (which will be an input to this block).
Does your IP provide enable signal for that inout port?.
---------- Post added at 17:10 ---------- Previous post was at 17:06 ----------
How many components are you using and how many inouts are you trying to connect to?.
Is it like this?
component IP is
some_sig : inout std_logic_vector(7 downto 0);
end component
component XXX is
gdata : inout std_logic_vector(7 downto 0);
idata : inout std_logic_vector(7 downto 0);
io_en : in std_logic;
clk : std_logic;
end component
MMM...so the enable signal you use to connect these two inout pins, takes 3 clks cycles to latch...and is that what you mean?.
yes - that what i mean to.
i am trying to find out a method to latch the data and plotit to/from the gdatainout port with 2 clocks -- look realizable ?
First answer me clearly this
Ques 1: How many inouts do you have which maps to pin-outs of the FPGA such as (qdata, idata, etc)?.I mean TOP-LVL ENTITY
Ques 2: How many components (ONLY THE ONES WHICH USE INOUT)are you using under your top-level module (such as IP, xxx, etc)?.
Ques 3: How do you wish to now connect the inouts from top-level to these components. CAN U SHOW SOMETHING LIKE A DIAGRAM\FLOW?.
Eg.,
top <--> Comp1 (IP)
top <--> Comp2 (XXX)
or
Top --> Comp1 (IP)
Top <-- Comp2 (XXX)
or so?...
Got it?
Please give a correct answer to these questions clearly?. Problem is not your English but how you frame words to give technical explanation which is little bit tough for me to get it.
ok i will try better to let you understand me
my fpga have to be connected to DSP.
the busses i have -
gdata ; inout
gaddress ; in
wr_en ; in
rd_en ;in
ackmoledge ; out
from the PLB to the IPS u have no problem to connect the inout because i generate state machine that know to detect in or out and direct the data accordingly
Good explanation. I can understand better now. One more doubt\clarification.
What I understood was that you were trying to build some sort of soft processor like thing. Did you use microblaze in this case?. Since I remember PLBs and some IPs you said looked more like they were from EDK environment.
Okay let that be....no issues.
You said all IPs have inout port, how are they mapped? and what signal is that inout port (an addr or data etc?)?.
If inout of all IPs are addr\data, how are you mapping and sharing same address port for all IP's through PLB bus?. Using an FSM to switch between read\write mode for each componenet?.
Let me speak more in coding style.
1) The gdata which is an inout coming from DSP, will be shared\connected to PLB. But is it also shared to all IPs????. Or the output of PLB(Which is also an inout) is shared to all other IPs?.
2) From PLB to all IPs, which inout bus are you sharing?. Same gdata inout from DSP?.Or any other inout port from PLB?. Make sure.
3) How do you connect gdata inout port to PLB?. Just direct portmapping?. Well, if direct port mapping means, the PLB can handle the inout internally...Chk that
4) In Xilinx PLB datasheet, I couldnot find PLB using any inout ports after all. Then how do you connect gdata to PLB bus first?. Are you using any enable? or so..and latching to input and output ports based on that?
can you be more specific here?. this is the place where you are having problems.
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