There is a port declared as inout port in my module. How can we connect an input and also an output to the same inout pin in that module? Please write the relevant RTL in Verilog while replying.
That means there will have to be an enable signal. Is it that there will have to be an enable signal for an inout? Can we write the rtl in somewhat the following manners so that the 1'bz can be eliminated?
assign bidir_pin = out_oe ? out_sig : in_put;
or
assign bidir_pin = out_en ? in_put : bidir_pin
Can you please write the rtl using the always block as stated by you?
That means there will have to be an enable signal. Is it that there will have to be an enable signal for an inout? Can we write the rtl in somewhat the following manners so that the 1'bz can be eliminated?
You can't get rid of the 1'bz That is the state of the output when it's not enabled. Draw the schematic of a bidirectional driver.
What you are want to implement ends up being a latch.
Can you please write the rtl using the always block as stated by you?
I created this ascii art to put in my verilog code near any tristate instances to remind myself visually what is occurring....
keep in mind, this should be used with mono-spaced fonts, it will not make sense without one....enjoy...