inout port connection to input and output

[sun_ray]

There is a port declared as inout port in my module. How can we connect an input and also an output to the same inout pin in that module? Please write the relevant RTL in Verilog while replying.

Regards

 

[ads-ee]

That inout port better be a top level port that is a bidirectional pin. You shouldn't be using submodules with inout ports.

With that said.

---

Code Verilog - [expand]
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module bidir_io (
  inout   bidir_pin
);
 
  wire out_oe;
  wire out_sig;
  wire in_sig;
 
  assign bidir_pin = out_oe ? out_sig : 1'bz;
 
  assign in_sig = bidir_pin;
 
endmodule

---

You could also have clocked always blocks instead of continuous assignments

Regards

 

[sun_ray]

That inout port better be a top level port that is a bidirectional pin. You shouldn't be using submodules with inout ports.

With that said.

---

Code Verilog - [expand]
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module bidir_io (
  inout   bidir_pin
);
 
  wire out_oe;
  wire out_sig;
  wire in_sig;
 
  assign bidir_pin = out_oe ? out_sig : 1'bz;
 
  assign in_sig = bidir_pin;
 
endmodule

---

You could also have clocked always blocks instead of continuous assignments

Regards

That means there will have to be an enable signal. Is it that there will have to be an enable signal for an inout? Can we write the rtl in somewhat the following manners so that the 1'bz can be eliminated?

assign bidir_pin = out_oe ? out_sig : in_put;

or

assign bidir_pin = out_en ? in_put : bidir_pin

Can you please write the rtl using the always block as stated by you?

Regards

 

[ads-ee]

That means there will have to be an enable signal. Is it that there will have to be an enable signal for an inout? Can we write the rtl in somewhat the following manners so that the 1'bz can be eliminated?

assign bidir_pin = out_oe ? out_sig : in_put;

or

assign bidir_pin = out_en ? in_put : bidir_pin

Regards

You can't get rid of the 1'bz That is the state of the output when it's not enabled. Draw the schematic of a bidirectional driver.
What you are want to implement ends up being a latch.

Can you please write the rtl using the always block as stated by you?

Come on, you really needed my help to write this?

---

Code Verilog - [expand]
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always @ * bidir_pin <= out_oe ? out_sig : 1'bz;
// or with an if
always @ * if (out_oe) bidir_pin <= out_sig; else bidir_pin <= 1'bz;

---

Regards

 

[StanDarsh18]

I created this ascii art to put in my verilog code near any tristate instances to remind myself visually what is occurring....
keep in mind, this should be used with mono-spaced fonts, it will not make sense without one....enjoy...

[FONT=Courier New]
//====================================================================================
//            en --                             
//                |                             
//                |                             
//              |\|  <-- bi-directional port -->
// sig_out -->__| \_____________________________
//              | /           |     sig_io      
//              |/            |                 
//                            |                 
//   sig_in   <-- ____________|                 
//  
//   VERILOG CODE:
// 
// 
// assign sig_io = (en) ? sig_out : {DATAWIDTH{1'bz}};      //DATAWIDTH = size of bus
// assign sig_in = sig_io ;  
//
//=====================================================================================[/FONT]