Hi, now I want to compare the power consumption between the synthesized design (design compiler) and the post layout design (Innovus) based on a switching activity file. The first one can be easily done by generating an .saif file from post synthesis simulation (requires synthesized netlist and .sdf file).
1. For the post layout activity file, I suppose I have to do the same simulation with post layout netlist and .sdf file (these are the only two ?) and this .sdf should have extracted parasitic delays ?
2. Innovus does not seem to accept .saif for report_power (does for VCD). If I use the .vcd for that, would the power comparison be 1 to 1 ?
Thanks