rrucha
Member level 3
I have an error detection code which has a generator and a receiver. The receiver checks if there were any errors while transmission. I have a testbench, where I plan to add an error injecting mechanism. I want to add errors at random places. Is there a specific way to do it?
I was thinking of making a module in the test bench that will flip one random bit in the data that is received. Is this the right way to implement random error injection in SystemVerilog? If not, how else can I do it?
I was thinking of making a module in the test bench that will flip one random bit in the data that is received. Is this the right way to implement random error injection in SystemVerilog? If not, how else can I do it?