Initialising memory outside a module

[abionnnn]

Hi guys,

lets say I've created a module called rom16_8 below:

module rom16_8(address, data);
  input [7:0] address;
  output [15:0] data;
  reg [15:0] memory [255:0];

  assign data = memory[address];

Lets say I was to initialise this from a test bench, tb_rom16_8, how would I initialise memory?\]

 

[FvM]

Normally, ROM has to be intialized for synthesized code, either from a file or in an init block. Why not use the same initialisation in the test? It's part of the design and should be tested in the simulation anyway.

Apart from this standard method, a ROM can be forced in a testbench as any signal.

 

[abionnnn]

How can you force it in a testbench, out of interest? (the syntax)

can I say

rom16_8 myrom (.address(blah1), .data(blah2))

$readmemb("rom.bin",myrom.memory)

?