garvind25
Full Member level 3
Hi there,
I am looking to start of in DFT domain. I needed the following info pls.
*Is it OK to work on DFT domain with VHDL as an HDL language (instead of Verilog). Also, what would
be the merits / demerits of using VHDL to verilog (except for Verilog is simpler to learn).
*I need some tools for synthesis, scan chain insertion and test pattern generation. Does anyone
know of free tools available to substitute for Synopsys Design Compiler and TetraMax. I am asking
his as I am planning to learn at my personal level and hence cannot purchase the softwares.
Thanks,
Arvind Gupta.
I am looking to start of in DFT domain. I needed the following info pls.
*Is it OK to work on DFT domain with VHDL as an HDL language (instead of Verilog). Also, what would
be the merits / demerits of using VHDL to verilog (except for Verilog is simpler to learn).
*I need some tools for synthesis, scan chain insertion and test pattern generation. Does anyone
know of free tools available to substitute for Synopsys Design Compiler and TetraMax. I am asking
his as I am planning to learn at my personal level and hence cannot purchase the softwares.
Thanks,
Arvind Gupta.
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