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[SOLVED] Information about DDS AD9915

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ali ghafoor

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Salam,
How to extract the required power of REFERENCE CLOCK needed to operate AD9915 IC. I am using PLL enabled mode. EXTERNAL REFERENCE CLOCK is of 100 MHz and a multiplier of 24 is being used, hence system frequency is 2400 MHz. what is the minimum and maximum ratings of power for EXTERNAL REFERENCE CLOCK. Kindly help me out . Datasheet of AD9915 is attached. I was unable to extract this information from Datasheet.
 

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The datasheet specifies 632mV-pp of minimum differential drive, but that's not a complete answer. The real answer depends on the clock source. Is it single ended or differential? Do you plan on terminating or impedance matching to the ref clk port? Is the clock a sine or square wave?

632mV-pp into a single ended 50ohm termination is exactly 0dBm (no coincidence I'm sure). If you use a 1:2 balun terminated in 100ohms you could get away with -3dBm. If you impedance match directly to the input impedance of the pins, then it could be much less.
 
The datasheet specifies 632mV-pp of minimum differential drive, but that's not a complete answer. The real answer depends on the clock source. Is it single ended or differential? Do you plan on terminating or impedance matching to the ref clk port? Is the clock a sine or square wave?

632mV-pp into a single ended 50ohm termination is exactly 0dBm (no coincidence I'm sure). If you use a 1:2 balun terminated in 100ohms you could get away with -3dBm. If you impedance match directly to the input impedance of the pins, then it could be much less.


I am using the evaluation board provided by analogue devices. It assumes a single-ended reference Clock and then converts the single-ended clock into differential clock using a clock buffer ADCLK925. And Ad9915 is fed with converted differential clock. Now, can I apply a sinewave reference clock of +10dBm to this evaluation board without damaging the AD9915.
 

Okay, so your question is about driving the ADCLK925, not the ADD915...

On the eval board schematic VT of the ADCLK925 is connected to Vref, which should be 2.15V, so the D input will be biased there. The datasheet specifies an absolute max input voltage range of Vee-0.5V to Vcc+0.5V. So with that bias the IC can take an amplitude of 2.65V, or 1.88Vrms for a sinewave, which is +18.5dBm. So yes, a +10dBm input should work fine.
 

Okay, so your question is about driving the ADCLK925, not the ADD915...

On the eval board schematic VT of the ADCLK925 is connected to Vref, which should be 2.15V, so the D input will be biased there. The datasheet specifies an absolute max input voltage range of Vee-0.5V to Vcc+0.5V. So with that bias the IC can take an amplitude of 2.65V, or 1.88Vrms for a sinewave, which is +18.5dBm. So yes, a +10dBm input should work fine.

I am using evaluation board of AD9915, and not that of ADCLK925 (It seems from your answer that you perceived that i am using the evaluation board of ADCLK925). Evaluation board of AD9915 uses an on-board IC of ADCLK925 to convert the single-ended refernce clock into differential.
 

I am using evaluation board of AD9915, and not that of ADCLK925 (It seems from your answer that you perceived that i am using the evaluation board of ADCLK925).
No I'm looking at the documentation for the AD9915 eval board. But since you're directly driving the ADCLK925, you're more concerned with the ADCLK925 specifications.
 

OK. Got your answer. Thanks

- - - Updated - - -

@mtwieg:

Just want to clear one thing, so the reader of this post does not get confused later on. Maximum input range for ADCLK925 is Vcc+0.5 V , that is equal to 3.8 Volts. So the input at D pin can take an amplitude of 3.8-2.15=1.65V (Vpeak-Vref). But you mentioned it to be 2.65V. Kindly correct me if I am wrong
 

Yeah I think you're right, for some reason I assumed that Vcc was 5V instead of 3.3V. In that case the max amplitude should be 1.65V. But personally I would try to keep the input voltage between Vee and Vcc, meaning amplitude would be 1.15V max.
 

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