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Info about four corner STA

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rakko

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hey, anybody knows why do 4 corner timing analysis? seems to me worst/worst and best/best should tell you if you have any setup or hold violations in the extreme corners of your design!
 

stormwolf

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four corner sta

Now, OCV ( on chip variant) timing analysis should do. because sometimes PVT in chip isn't a constant.
It will analyse some worst/best or best/worst.

Added after 1 minutes:

We usally do best, worst , typical and OCV analyse.
 

jitendra

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Re: four corner sta

According to my knowledge, four corner STA means:
1. Setup Worst - setup timing in slow corner
2. Setup Best - setup timing in fast corner
3. Hold Best - hold timing in fast corner
4. Hold Worst - hold timing in slow corner

Hope this is helpful.
 

rkadarla

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Re: four corner sta

I beleive that the four corners of the STA would other wise be

1.BC- WC ( best case - worst case)
2. OCV ( on chip variation, by introducing Time derating)
3.CRPR ( Clock Reconvergence Pessimism Removal)
4. Single mode or Multimode timing analysis.

:idea::|
 

mohdfayez

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Re: four corner sta

tats perfectly right answer Ravi :D ;)
 

Thinkie

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four corner sta

I don't see the point in doing OCV without CRPR....

If you do, then you may end up inserting more buffers that you really need to fix OCV problems that don't really exist
 

rakko

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Re: four corner sta

you all missed my question. I know the simple definition and from the posts, it seems that everyone else understands this too!.
Now lets push a little deeper. If we do our timing analysis at slow-slow and fast-fast. We are assured that we covered the two extreme corners and therefore have analyzed everything in between these two corners. Namely slow-fast and fast-slow. Since the PVT at slow-slow corner are the highest and in fast-fast are the lowest it ever can be. It is not possible to find a setup problem in slow-fast that slow-slow analysis missed. Now, the question "Why bother with the two middle cases?"
 

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Re: four corner sta

Hi,

As per my understanding to STA, It is possible to find setup violations in slow-fast case which missed in other cases(slow data path and the fast clock path), similarly hold violations in other case.

Correct me if i am wrong.
 

lostinxlation

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Re: four corner sta

Four corner checking is the combination of slow or fast corner for P channel and slow or fast corner for N channel.. At least that's the definition our circuit design team had long time ago.

There are cases that SF corner(S: P channel, F: N channel) can be more prone to hold viols than FF.
For example, consider the path that is made with the series of transmission gates. Clock tree is made with buffers or inverters, where both of P channels and N channels are equally exercised, so that SF corner gives you larger clock skew than FF corner. Now suppose the data path has many transmission gates connected serially. As you know, P channel of transmission gate doesn't contribute to the delay much since the major role of P channels in the transmission gates is just pulling up the node voltage beyond the threshold of N channel. So, the delay of transmission gates heavily depends on N channels where the fast corner is used for.
In this scenario, you have larger clock skews, but not much change on data path delay, comparing to FF corner. What does it mean ? Apprarently, it means SF corner is more prone to the hold violation than FF.
 
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