Inferring ram in fpga

[nico24]

I am using an Altera Cyclone IV EP4CE6E22C8. I am trying to infer, I guess block ram, to use the FPGA memory resources, instead of the logic resources.

In order to get correct timing with the 6502 CPU module (arlet) I have used the following code:

module rom2716_a
(
    input [10:0] addr,
    output [7:0] q // reg
);

    reg [7:0] rom[2047:0];

    initial
    begin
        $readmemh("rom1a.txt", rom);
    end

    assign q = rom[addr];

endmodule

This will not use the memory resources when compiled, as I assume it is not 'recognized' as bram.

If I use the following code, as then it does use the memory resources of the FGPA, however, the timing is too late to be useful with the 6502 CPU module.

module rom2716_a2
(
    input [10:0] addr,
    input clk,
    output reg [7:0] q
);

    reg [7:0] rom[2047:0];

    initial
    begin
        $readmemh("rom1a.txt", rom);
    end

    always @ (posedge clk)
    begin
        q <= rom[addr];
    end

endmodule

Is there anything I can do to keep the timing of the first, but to get it using FPGA memory resources?
FYI I'm using the same clk timing for the CPU and the memory - maybe it's possible to use a higher frequency clk to get the timing earlier.

Thanks,

Nico

 

[FvM]

FPGA block RAM is synchronous RAM, in case of ROM mode, you have an address register that can't be bypassed.

Respectively the first clock-less design can't infer block RAM. I read that the arlet 6502 core expects synchronous memory (as any CPU softcore dedicated to FPGA). Thus I think, you only have designed your ROM interface inappropriately.

 

[nico24]

Thanks - I should read the arlet 6502 documentation! It certainly works with asynchronous rom, but maybe not how it's supposed to be.
Thanks for the pointer!

 

[bansalr]

I am using an Altera Cyclone IV EP4CE6E22C8. I am trying to infer, I guess block ram, to use the FPGA memory resources, instead of the logic resources.

In order to get correct timing with the 6502 CPU module (arlet) I have used the following code:

module rom2716_a
(
    input [10:0] addr,
    output [7:0] q // reg
);

    reg [7:0] rom[2047:0];

    initial
    begin
        $readmemh("rom1a.txt", rom);
    end

    assign q = rom[addr];

endmodule

This will not use the memory resources when compiled, as I assume it is not 'recognized' as bram.

If I use the following code, as then it does use the memory resources of the FGPA, however, the timing is too late to be useful with the 6502 CPU module.

module rom2716_a2
(
    input [10:0] addr,
    input clk,
    output reg [7:0] q
);

    reg [7:0] rom[2047:0];

    initial
    begin
        $readmemh("rom1a.txt", rom);
    end

    always @ (posedge clk)
    begin
        q <= rom[addr];
    end

endmodule

Is there anything I can do to keep the timing of the first, but to get it using FPGA memory resources?
FYI I'm using the same clk timing for the CPU and the memory - maybe it's possible to use a higher frequency clk to get the timing earlier.

Thanks,

Nico

Just check enable and all other pins...

always @ (posedge clk)
begin
if (en)
q <= rom[addr];
end


Try this it should work...Otherwise generate a code using IP generator....