nico24
Newbie
I am using an Altera Cyclone IV EP4CE6E22C8. I am trying to infer, I guess block ram, to use the FPGA memory resources, instead of the logic resources.
In order to get correct timing with the 6502 CPU module (arlet) I have used the following code:
This will not use the memory resources when compiled, as I assume it is not 'recognized' as bram.
If I use the following code, as then it does use the memory resources of the FGPA, however, the timing is too late to be useful with the 6502 CPU module.
Is there anything I can do to keep the timing of the first, but to get it using FPGA memory resources?
FYI I'm using the same clk timing for the CPU and the memory - maybe it's possible to use a higher frequency clk to get the timing earlier.
Thanks,
Nico
In order to get correct timing with the 6502 CPU module (arlet) I have used the following code:
Code:
module rom2716_a
(
input [10:0] addr,
output [7:0] q // reg
);
reg [7:0] rom[2047:0];
initial
begin
$readmemh("rom1a.txt", rom);
end
assign q = rom[addr];
endmodule
This will not use the memory resources when compiled, as I assume it is not 'recognized' as bram.
If I use the following code, as then it does use the memory resources of the FGPA, however, the timing is too late to be useful with the 6502 CPU module.
Code:
module rom2716_a2
(
input [10:0] addr,
input clk,
output reg [7:0] q
);
reg [7:0] rom[2047:0];
initial
begin
$readmemh("rom1a.txt", rom);
end
always @ (posedge clk)
begin
q <= rom[addr];
end
endmodule
Is there anything I can do to keep the timing of the first, but to get it using FPGA memory resources?
FYI I'm using the same clk timing for the CPU and the memory - maybe it's possible to use a higher frequency clk to get the timing earlier.
Thanks,
Nico