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Inequality operator in VHDL

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nizdom

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Hi guys. I've read that the inequality operator /= can be used inside an IF statement. My scenario is if let's say ASSIGNMENT is an Integer array of 4 from 0 to 3, and if none in the array has a value of 0 let's say ASSIGNMENT = [2 3 1 1], then I would assign a certain signal a bit vector value of "00". But I am trying the inequality operator like "if ASSIGNMENT(0) /= 0 AND ASSIGNMENT(1)/= 0 . . . and so on but it's not working. Any help?
 

FvM

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but it's not working
Useless report. As far I'm aware of it's legal VHDL syntax, otherwise you should post the respective syntax error message. We can't know why your code hasn't the intended effect if you don't show it.
 

TrickyDicky

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if you're checking that any entry in the array is 0, then why not use the equality and an OR operator?


Code VHDL - [expand]
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if A(0) = 0 or A(1) = 0 or A(2) = 0 or A(3) = 0 then
  OP <= "00";
end if;

 

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