increasing the clock frequency of vertex5 in AES

[sougata_vlsi13]

I have written the code of AES and after that i got the synthesis report.In that report the clock frequency is coming as near about 51.43MHz,but i want to increase the clock frequency.Is it possible to increase the frequency.What i need to do for that...please help me

 

[sivamani]

What is 51.43MHz ?Is it max operating freq of that logic or you are deriving this clock from a reference clock?

If you want to run your logic at higher frequency then set the timing constraint in the UCF.

 

[sougata_vlsi13]

What is 51.43MHz ?Is it max operating freq of that logic or you are deriving this clock from a reference clock?

If you want to run your logic at higher frequency then set the timing constraint in the UCF.

Yes sir it is the maximum operating frequency.Sir i am lil bit newer in the FPGAs,so i will be highly thankful if you kindly tell me how to set the timing constraint in UCF.

 

[sivamani]

refer

**broken link removed**

syntax is (below time spec is for 50MHz)

NET "refclk_50mhz" TNM_NET = "refclk_50mhz";
TIMESPEC "TS_refclk_50mhz" = PERIOD "refclk_50mhz" 20.00 ns HIGH 50 %;

 

[sougata_vlsi13]

Sir I did the same way in which you suggested.I give the timing specification in period column as 500 ns and one corresponding UCF file has been generated.but in par report it is showing no change...one msg is coming like that

ar:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high.

so what should i do now.

- - - Updated - - -

anyway sir,the previous problem got solved but in the synthesis report i am getting the operating frequency as previous one only...

 

[sivamani]

Enable the timing constraints option in PAR settings.looks like presently it is disabled.see this

282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x").

On what frequency you would like to run your code? 500ns is only 2MHz.

 

[sougata_vlsi13]

Enable the timing constraints option in PAR settings.looks like presently it is disabled.see this

282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x").

On what frequency you would like to run your code? 500ns is only 2MHz.

sir i want to run the code on 200 MHZ../.

 

[sivamani]

Then it is 5ns not 500ns

 

[TrickyDicky]

sir i want to run the code on 200 MHZ../.

If the timing analyser is telling you that the FMax is 51MHz without any timing specs, then there is a problem with your code, not your timing specs. You need to add a lot more pipelining if you want this thing to run at 200MHz.