[SOLVED] Increasing NWELL size in layout - hierarchy

[The_Dutchman]

Hello all,

For my specific problem I need to increase some PMOS NWELL sizes from the PDK transistors. In my simulations I always used 5 terminal PMOS (S G D B PSUB) devices.
However in the layout, there is already a guard ring around the nwell, leaving no option to draw a bigger NWELL.

I tried to use a 4 terminal PMOS (without PSUB) in layout , then draw a bigger NWELL and do LVS. However there is a transistor mismatch (4 terminal vs 5 terminal). I can fix this by also putting the 4 terminal PMOS in my schematic, but then I don't have any PSUB connection anymore?

I don't see how I should fix this hierarchy issue? Should I use the 5 terminal model, flatten, and edit? Cause I don't like flatting the models from the PDK. Furthermore, how can I ensure to still get good PEX results?
Please help!

 

[kenambo]

Hi..

You can try using PCELLS or use the four terminal device and draw an additional PSUB guard ring by yourself.

Actually the five terminal device you mentioned must be drawn like this...so no problem to use four terminal device unless both 4 and 5 terminal devices have same properties..

 

[The_Dutchman]

Using a 4-terminal device and drawing the guard ring myself indeed solved the problem. However I had to add a floating substrate connection pin in the schematic for the LVS.