Re: [Synthesis] increasing clock frequency vs adding clock uncertainty
Well it depend on a lot of things like the source of clock, layout, components etc. Introducing 20% uncertainty in clock may cause setup and hold time violations in circuit.
Re: [Synthesis] increasing clock frequency vs adding clock uncertainty
There is some difference between increase the clock frequency and uncertainty.
For the touching of Freq, it will just have influence on setup timing check.
While the touching of uncertainty will have influence on both setup and hold timing check. And you have the opportunity to make the two different (see the options of set_clock_uncertainty command)
Re: [Synthesis] increasing clock frequency vs adding clock uncertainty
It is good to keep in mind that constraints play a role throughout design phase. So, it maynot be a good practice to just think of synthesis phase and resort to major modifications in later Physical implementation and Sign off stages. Though it is not relevant in Synthesis stage as in this thread, for crosstalk timing analysis, clock periods are very important to find out aggressor/window overlap etc. So, varying of uncertainty is considered a better option than fiddling with clock periods to over constraint. Uncertainty number is a factor that indeed is varied (across design stages and block/top level).
I had once compiled a list of things to remember when someone thinks of clock... Here it is.... It may not be relevant to the question,per se. But I have seen most clock related questions can be well understood if ALL these factors are kept in mind. View attachment clocks_check_list_fm_chowki.pdf