increase driving strength

[ludan]

Hi guys,

I think this is a very simple question for you but it's driving me crazy :-(

I'm synthesizing a design where I send out a negated version of the clock.
Let's assume this is a counter that has an assignment like:
assign clk_out = !clk;

of course this is translated with an inverter:
CNIVX3 U21 ( .A(clk), .Z(clk_out) );

As you can see the drive strength of that cell is 3 (after the X)
Is there a way to force the synthesizer to choose a much higher drive strength
for that cell? (in the library I'm using there are up to X124, for the inverter)

Thanks for any help

D

 

[Nantha]

Hi

I cant understand properly.. U mean drive load(Fan_out)? By changing the W/L ratio we cant get better drive load... Is it?

Rgds,
Nantha

 

[alaparthi]

yes, you should be able to set the drive strength

Please refer to:
**broken link removed**

 

[rca]

you need to understand why the tool have choose this drive.

the tool choose a drive function of the load to drive, and timing constraints.

So you must check your constraints before to increase by default the drive capability of a gate.

 

[kumar_eee]

Selecting bigger drive strength cell can create many problems like setup violation. The tool may need to optimize the circuit to remove the setup violation. This may increase the instance count, wire lengths, Core utilization, placement & routing congestion, power consumption and leakage etc.

 

[semi_jl]

Generally, the large driving stength cells in clock networks is not good, and is not recommended.
If you must use them, eg: x16, you can place it in your netlist and set it dont_touch. Or else, tools may change it to low size.

It should be the easy way.