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Driving multiple (digital) gates

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Full Member level 2
May 18, 2018
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I have 1 NAND that need to drive 32 NORs and am using the available standard cells.
i am not sure with theShould I use larger NAND available in the library or design a buffer (even-numbered INV in series with increasing size)?
I think I should use buffer but the design example that I have uses 1 NAND with unknown fanout capability.

Please excuse me with this basic question.
If I need to post it in the Digital thread instead, please let me know.
--- Updated ---

From a quick reading, I got that using larger gate increase the input cap that must be driven by the previous circuit obviously.

I still would like to hear some suggestions.
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A family of logic IC's has a certain amount of fanout capability. Different for TTL, CMOS, Low power Schottky, etc. It depends on how much current one output stage can provide, versus how much current is drawn by the inputs.

So is there any which can drive 32 gates? Haven't heard of any. Maybe 5 or 10 max.

There are plenty of solutions. A 74ACT244 for example will drive +/- 24 ma. ACT input current is typically 100 nA. That’s capable of way more than 32 gates.
I'm missing any consideration of intended switching speed as determining parameter for CMOS fan-out.

Yes, the maximum switching speed and load capacitance is the main determination of the maximum fanout, as the CMOS input current is generally negligible.

There is a standard method in ASIC and FPGA work for building clock trees
to solve this type of problem.

Google "fpga clock tree design", tons of ref material.

Other approaches -

Regards, Dana.

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