include library in a verilog file

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dengelpolar

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i met a 'unexpected' error while including a library in a verilog file.

****************verilog file*************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
************************************

and when i compiled thie file , i met
Error: E:/ModelSim/Modelsim10/examples/taxi.v(6): near ";": syntax error, unexpected ';', expecting STRING_LITERAL

what is the problem?

thank you for any help~
 

You are trying to include VHDL standard libraries in Verilog.

The library and use keywords are unknown in Verilog.
 
aha, grate for your help.

is there any way to use the ieee libarary in Verilog? or i'd best found a new VHDL file to do my job?

- - - Updated - - -

rajavel.rv said:
u can save that vhdl coding for seprate file ____.vhd and call that entity to component of the ur verilog file; don't compile ur _____.v file inside of vhdl coding....
Click to expand...

o yes, thank you very much!
 

Verilog has no libraries. The IEEE specs for 1164 are built into the verilog language (1,0, Z and X). Std_logic_unsigned is NOT an IEEE library.
 
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