Include C program testbench files in VHDL project

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Sunayana Chakradhar

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Hi,

I have a VHDL project, but the testbench is written in C program. How do I include this C program testbench file in the project so that i can simulate it?
 

What tools have you got to run this simulation?
 

Im fairly confident you cannot use the ISE simulator for C simulation. You might be able to do it with a full version of modelsim.
 

Is it really a C testbench that interacts with the VHDL code during run time? or just a C model that generates test vectors?

The former would be quite a rare thing (and I suggest speaking to the original author to see how (s)he got it working)
 

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