Include C program testbench files in VHDL project

[Sunayana Chakradhar]

Hi,

I have a VHDL project, but the testbench is written in C program. How do I include this C program testbench file in the project so that i can simulate it?

 

[TrickyDicky]

What tools have you got to run this simulation?

 

[Sunayana Chakradhar]

I have Xilinx ISE 14.7 version

 

[TrickyDicky]

Im fairly confident you cannot use the ISE simulator for C simulation. You might be able to do it with a full version of modelsim.

 

[Sunayana Chakradhar]

okay which all tools do I need for this program to run?

 

[TrickyDicky]

Is it really a C testbench that interacts with the VHDL code during run time? or just a C model that generates test vectors?

The former would be quite a rare thing (and I suggest speaking to the original author to see how (s)he got it working)