sdf-3250
Yes, you are right.
this is my flow:
1. compile testbench.v and mips_struct.v
these two files are all verilog files. mips_struct.v is generated by design compiler. mips_sturct.v is a structural file.
2: compile mips_struct.sdf file which is generated by design compiler
sdfcom mips_struct.sdf mips_struct_output.sdf
3: vsim -novopt -sdftyp /top/dut/=mips_struct.sdf work.top
after that, however, there are a lot of errors.
like this:
Error: (vsim-3033) /home/lv/Desktop/modelsim/mips_struct.v(100): Instantiation of 'DFFX1' failed. The design unit was not found.
# Region: /top/dut
# Searched libraries:
# /home/lv/Desktop/modelsim/work
and here "DFFX1" is the name of DFF in my library(mips_lib.db file)
So, should I compile this library file? and how to compile it?
many thanks
Added after 35 minutes:
when the gate level above fails, i do the register level simulation, however, it generates the following errors.
---------------------------------------------------------------------------------------------------------------
# ** Error: (vsim-SDF-3250) mips_struct.sdf(18): Failed to find INSTANCE '/top/dut/U853'.
# ** Error: (vsim-SDF-3250) mips_struct.sdf(19): Failed to find INSTANCE '/top/dut/U852'.
# ** Error: (vsim-SDF-3250) mips_struct.sdf(20): Failed to find INSTANCE '/top/dut/U851'.
# ** Error: (vsim-SDF-3250) mips_struct.sdf(21): Failed to find INSTANCE '/top/dut/U851'.
# ** Error: (vsim-SDF-3250) mips_struct.sdf(22): Failed to find INSTANCE '/top/dut/U850'.
# ** Warning: (vsim-SDF-3432) mips_struct.sdf: This file is probably applied to the wrong instance.
# Ignoring subsequent missing instances from this file.
# ** Warning: (vsim-SDF-3441) mips_struct.sdf: Failed to find 2831 out of the 2832 instances from this file.
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "mips_struct.sdf".
# Time: 0 ps Iteration: 0 Region: /top File: /home/lv/Desktop/modelsim/mips-test.v
---------------------------------------------------------------------------------------------------------------
and this is part of my sdf file.
(DELAYFILE
(SDFVERSION "OVI 1.0")
(DESIGN "mips")
(DATE "Thu Dec 11 20:00:56 2008")
(VENDOR "foo")
(PROGRAM "Synopsys Design Compiler cmos")
(VERSION "Z-2007.03-SP4")
(DIVIDER /)
(VOLTAGE 5.00:5.00:5.00)
(PROCESS)
(TEMPERATURE 25.00:25.00:25.00)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "mips")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT U384/Y U853/A (0.000:0.000:0.000))
(INTERCONNECT U378/Y U852/A (0.000:0.000:0.000))
(INTERCONNECT U721/Y U851/A (0.000:0.000:0.000))
(INTERCONNECT U797/Y U851/B (0.000:0.000:0.000))
U853,U852,U851 are indeed in the sdf file. I do not know why it said cannot find them.
many thanks.
Added after 54 minutes:
Oooo, sorry, guys.
I made a mistake. I used the old sdf file instead the compiled sdf file.
vsim -novopt -sdftyp /top/dut/=mips_struct.sdf
I should use:
vsim -novopt -sdftyp /top/dut/=mips_struct_out.sdf
Now, all the errors are gone. But there is still another critical problem.
here is the error messages:
vsim -novopt -sdftyp /top/dut/=mips_struct_out.sdf work.top
# vsim -sdftyp /top/dut/=mips_struct_out.sdf -novopt work.top
# Loading work.top
# Loading work.mips
# ** Warning: (vsim-3009) [TSCALE] - Module 'mips' does not have a `timescale directive in effect, but previous modules do.
# Region: /top/dut
# Loading work.DFFX1
# ** Warning: (vsim-3009) [TSCALE] - Module 'DFFX1' does not have a `timescale directive in effect, but previous modules do.
# Region: /top/dut/dp_mdr_q_reg_0_
# Loading work.AOI4
# ** Warning: (vsim-3009) [TSCALE] - Module 'AOI4' does not have a `timescale directive in effect, but previous modules do.
# Region: /top/dut/U2
# Loading work.OAI3
# ** Warning: (vsim-3009) [TSCALE] - Module 'OAI3' does not have a `timescale directive in effect, but previous modules do.
# Region: /top/dut/U3
# Loading work.NOR2X1
# ** Warning: (vsim-3009) [TSCALE] - Module 'NOR2X1' does not have a `timescale directive in effect, but previous modules do.
# Region: /top/dut/U155
# Loading work.NAND3X1
# ** Warning: (vsim-3009) [TSCALE] - Module 'NAND3X1' does not have a `timescale directive in effect, but previous modules do.
# Region: /top/dut/U158
# Loading work.INVX4
# ** Warning: (vsim-3009) [TSCALE] - Module 'INVX4' does not have a `timescale directive in effect, but previous modules do.
# Region: /top/dut/U153
# Loading work.NAND2X2
# ** Warning: (vsim-3009) [TSCALE] - Module 'NAND2X2' does not have a `timescale directive in effect, but previous modules do.
# Region: /top/dut/U175
# Loading work.NAND2X1
# ** Warning: (vsim-3009) [TSCALE] - Module 'NAND2X1' does not have a `timescale directive in effect, but previous modules do.
# Region: /top/dut/U166
# Loading work.INVX1
# ** Warning: (vsim-3009) [TSCALE] - Module 'INVX1' does not have a `timescale directive in effect, but previous modules do.
# Region: /top/dut/U414
# Loading work.BUFX8
# ** Warning: (vsim-3009) [TSCALE] - Module 'BUFX8' does not have a `timescale directive in effect, but previous modules do.
# Region: /top/dut/U715
# Loading work.BUFX4
# ** Warning: (vsim-3009) [TSCALE] - Module 'BUFX4' does not have a `timescale directive in effect, but previous modules do.
# Region: /top/dut/U772
# Loading work.TIEHI
# ** Warning: (vsim-3009) [TSCALE] - Module 'TIEHI' does not have a `timescale directive in effect, but previous modules do.
# Region: /top/dut/U806
# ** Error: (vsim-3006) /home/lv/Desktop/modelsim/mips-test.v(10): Too many inherited module instance parameters.
# Region: /top
# Loading work.exmemory
# Error loading design
-----------------------------------------------------
contents of exmemory module:
module exmemory #(parameter WIDTH=8)
(input clk,
input memwrite,
input [WIDTH-1:0] adr,writedata,
output reg [WIDTH-1:0] memdata);
reg [31:0] RAM [(1<<WIDTH-2)-1:0];
wire [31:0] word;
initial
begin
$readmemh("memfile.dat",RAM);
end
always@(posedge clk)
if(memwrite)
case(adr[1:0])
2'b00: RAM[adr>>2][31:24]<=writedata;
2'b01: RAM[adr>>2][23:16]<=writedata;
2'b10: RAM[adr>>2][15:8]<=writedata;
2'b11: RAM[adr>>2][7:0]<=writedata;
endcase
assign word=RAM[adr>>2];
always@(*)
case(adr[1:0])
2'b00: memdata <=word[7:0];
2'b01: memdata <=word[15:8];
2'b10: memdata <=word[23:16];
2'b11: memdata <=word[31:24];
endcase
endmodule