important points in phase detector

[sridhara]

phase detector tspc

i am designing a phase detector using the tspc implementation of D flip flop...for PLL wat are the important constraints in designing the phase detector....

(ie)wat the key points which u have to take care so that the pll works fine....

 

[Fahmy]

I think , you have to check the dead-zone

 

[lijianheng]

Phase detection linear range & dead zone.

 

[dinesh agarwal]

there is also one more issue and you must look for

that is the min pulse width of the output when thre is no phase and fre difference

this must be enough for complete switching of the MOS

 

[rfsystem]

To add one more:

The ref and div input signals to the phase/frequency detector are not always 50% duty. So if the falling edge comes near the rising edge of the other input it could also introduce nonlinearity.


To add another one:

More for characterization. If both input edges are aligned, so zero phase difference, the delay or minimum on time could be a little longer than the minimum pulse if the phase delay is significant.


Until I forget:

Test for symmetry. If phase difference behavior is not truly symmetric all sigma-delta calculations will fail.


Please stop here: (until I spend too much time)