panos_papajohn
Member level 2
Hi everyone ,
Im trying to implement a parallel in/serial out shift register in VHDL. I have written this code but when I run the simulation the results are the expected ones. Can anyone help me understand how the shifting is created? This is my code and below is the result from the simulation.
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This code it was supposed to shift all the loaded data to the SO but instead I can get only the MSB. Any ideas?
Thanks in advance
Im trying to implement a parallel in/serial out shift register in VHDL. I have written this code but when I run the simulation the results are the expected ones. Can anyone help me understand how the shifting is created? This is my code and below is the result from the simulation.
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift is
port(C, SI, ALOAD : in std_logic;
D : in std_logic_vector(7 downto 0);
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
signal load: std_logic;
begin
process (C, ALOAD, D)
begin
if (ALOAD='1') then
tmp <= D;
for c in 8 downto 1 loop
load <= tmp(c-1);
SO <= load;
end loop;
end if;
end process;
end archi;
This code it was supposed to shift all the loaded data to the SO but instead I can get only the MSB. Any ideas?
Thanks in advance