library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift is
port(C, SI, ALOAD : in std_logic;
D : in std_logic_vector(7 downto 0);
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
signal load: std_logic;
begin
process (C, ALOAD, D)
begin
if (ALOAD='1') then
tmp <= D;
for c in 8 downto 1 loop
load <= tmp(c-1);
SO <= load;
end loop;
end if;
end process;
end archi;
process (C, ALOAD,D)
begin
if (ALOAD='1') then
tmp <= D;
elsif rising_edge(C) then
tmp <= tmp(6 downto 0) & '0';
SO <= tmp(7);
end if;
end;
process(clk)
begin
if rising_edge(clk) then
if ALOAD = '1' then
--do stuff
end if;
end if;
end process;
if rising_edge(C) then
if (SLOAD='1') then
tmp <= D;
else
tmp <= tmp(6 downto 0) & '0';
end if;
SO <= tmp(7);
end if;
Quite exepectable, if the LOAD signal isn't deasserted again.I only see the first bit in the output.
Of course SPI is basically a shift register, but some details have to considered. I suggest to study data sheet figure 1 and the related timing specification. Particularly pay attention to t1, t2, t6 and t10. (setup and hold times for DI and nCS). It clarifies, that both signals have to be set on the falling edge of SCK, or SCK has to be inverted on output. The mode operation is usually designated SPI mode 0 (referring to the original Motorola syntax).I know I was asking for a shift register, cause I thought that is how I could implement the SPI
In the first place, these timings are design constraints, that have to be kept. If delays are required, that the logic device can't generate by nature, they have to be implemented in a synchronous way.I know that you can't have delays in your code unless its a testbench file.
I suggested a method in my post explicitely. It's about using the negative clock edge. This would be my suggestion, if the 50 MHz sysclock is used for SCK. If SCK is generated in your logic, you can e.g. set DO on one clock edge and SCK on the next.So how Im I going to sent the data before checking the clock in order to meet the t1 specifications?
ENTITY AD5061 IS
PORT
(
-- Globale Signale
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
data : IN UNSIGNED(15 downto 0);
dav : IN STD_LOGIC;
DACCLK : OUT STD_LOGIC;
nCS_DAC : OUT STD_LOGIC;
MOSI : OUT STD_LOGIC
);
END AD5061;
ARCHITECTURE rtl OF AD5061 IS
SIGNAL sr : STD_LOGIC_VECTOR(23 downto 0);
SIGNAL bitcnt : INTEGER RANGE 0 TO 24;
SIGNAL DACCLKi : STD_LOGIC;
BEGIN
PROCESS (clk)
BEGIN
IF reset = '1' THEN
bitcnt <= 0;
nCS_DAC <= '1';
DACCLKi <= '0';
ELSIF rising_edge(clk) THEN
IF dav = '1' AND bitcnt = 0 THEN
DACCLKi <= '1';
sr <= x"00" & STD_LOGIC_VECTOR(data);
nCS_DAC <= '0';
bitcnt <= 24;
ELSIF bitcnt > 0 THEN
DACCLKi <= NOT DACCLKi;
IF DACCLKi = '0' THEN -- this is a rising edge
bitcnt <= bitcnt - 1;
IF bitcnt > 1 THEN
nCS_DAC <= '0';
sr <= sr(22 downto 0) & "0";
ELSE
nCS_DAC <= '1';
END IF;
END IF;
ELSE
DACCLKi <= '0';
END IF;
END IF;
END PROCESS;
DACCLK <= DACCLKi;
MOSI <= sr(23);
END rtl;
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