sanjana
Junior Member level 2

I am implementing a cache memory in FPGA.
for that i need a memory of 16 bytes wide and 256 entries.
I am implementing using VHDL.
the problem is I want to download in FPGA.
Is there any way to make effective utilization of area in FPGA in this application
for that i need a memory of 16 bytes wide and 256 entries.
I am implementing using VHDL.
the problem is I want to download in FPGA.
Is there any way to make effective utilization of area in FPGA in this application