Implementing cache algorithm for DSP chipset in Verilog

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fabiodeng

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cache algorithm

dear all :

recently i need to design a good cache algorithm for a small DSP chipset , I have no clue on which one is the best choice and the cost ( the trade off ) . Of course , I have even learnt the course : computer architect : quantative approach and have the read the corresponding section thoroughly at the book .

I am an IC design student and had to implemetn the algo. with VERILOG . Any examples or advice ?

Many thanks !



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