this is simple just put an AND gate at the DFF's preset signal and "and " the input signal and clock signal together.
Then put another and gate at the clear signal pin, "and" the invert input signal and also the clock signal.
This assume that, the control signal is active high and we use total of 3 gate: 2 and gates and 1 inverter.
But as phutanesv said, what for we need this conversation.
enable signal still the preset and also the clear signal just that we are no using the clk and input pin.
Mean we just use the preset and clear pin with the help of and gate and not gate
Din = E'Q+INE, Pr = (E'Q+INE)', Cr = E'Q+INE, clock = E.
where Din- input to D-flipflop
E- Enable input,
Q-present state of D-flipflop
IN-input signal
Pr-preset input
Cr-clear input