Take a look at the Xilinx SDSoC which uses Vivado HLS for Zynq devices.
To use it you don't need to know any HDL languages.
You need to select what a function you want to port to FPGA. The software translates it to a block with an AXI interface
This is possible only for the SDSoC platforms, which are already available on the market (check the list on the software site). You can also define your own platform for SDSoC, if you have a PCB with a Zynq device.
Node-Locked License cost is $995.
Sounds great?! The devil is always in the details...
You need to know a specific compiler pragmas to port functions properly to the FPGA.
Also it is good to know some HDL language and Zynq architecture to figure out how to fix possible timing issues in the FPGA project.