Implementation PRnoise with fpga by VHDL code

[gaffarnazari@yahoo.com]

Hi to all.can any one help me for implementation PR noise with fpga by VHDL code?

 

[TrickyDicky]

Yes. Post the code and what the problems are, and we can help Im sure.

 

[gaffarnazari@yahoo.com]

Hi.I simulate this code in ISE13,after that make project it has not error but when I make testbench it has some error.
this is my code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
USE std.textio.all;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS

COMPONENT noise_gen
Generic (
W : integer := 16; -- LFSR scaleable from 24 down to 4 bits
V : integer := 18; -- LFSR for non uniform clocking scalable
g_type : integer := 0; -- gausian distribution type, 0 = unimodal, 1 = bimodal, from g_noise_out
u_type : integer := 1 -- uniform distribution type, 0 = uniform, 1 = ave-uniform, from u_noise_out
);
PORT(
clk : IN std_logic;
n_reset : IN std_logic;
enable : IN std_logic;
g_noise_out : OUT std_logic_vector(W-1 downto 0);
u_noise_out : OUT std_logic_vector(W-1 downto 0)
);
END COMPONENT;

SIGNAL clk : std_logic;
SIGNAL n_reset : std_logic;
SIGNAL enable : std_logic;
SIGNAL g_noise_out : std_logic_vector(15 downto 0);
SIGNAL u_noise_out : std_logic_vector(15 downto 0);

-- Period for clock
constant PERIOD : time := 20 ns;

-- Used to open files to store data output
FILE f: TEXT OPEN WRITE_MODE IS "test_file_GD.txt";
FILE f1: TEXT OPEN WRITE_MODE IS "test_file_UD.txt";

BEGIN

-- Port mapping of unit under test
uut: noise_gen PORT MAP(
clk => clk,
n_reset => n_reset,
enable => enable,
g_noise_out => g_noise_out,
u_noise_out => u_noise_out
);

-- PROCESS TO CONTROL THE CLOCK
clock : PROCESS
-- variable used for file line number
VARIABLE file_line : LINE;

BEGIN
clk <= '1';
WAIT FOR PERIOD/2;
-- write ouptut to files
WRITE(file_line, conv_integer(g_noise_out));
WRITELINE(f, file_line);
WRITE(file_line, conv_integer(u_noise_out));
WRITELINE(f1, file_line);
clk <= '0';
WAIT FOR PERIOD/2;
END PROCESS;


-- *** Test Bench - User Defined Section ***
-- test vectors are put here
tb : PROCESS
BEGIN
enable <= '1';
n_reset <= '0';
WAIT FOR 40 NS;
n_reset <= '1';
WAIT FOR 4000 NS;

wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;

 

[TrickyDicky]

What are the errors?

 

[mrflibble]

Possibly try and keep it in 1 thread? I just noticed this one is about the exact some thing as your other thread. At any rate, please be more specific because we don't do mind reading around here. Errors? Expected results?

 

[gaffarnazari@yahoo.com]

I wrote lsfr code and simulated.I have another question;how can I programming si4136?how should I to write VHDL code?I have problem in write respectively vhdl code. please help me

 

[TrickyDicky]

post the code, post the problems, and we should be able to help. Your problem is too vague at the moment.