Implementation of BZFAD

[poornimayn]

can anyone post or upload VHDL code for BZFAD??...Its very critical for my project!..I need that as a reference code.

 

[rca]

did you expect we will do you homework?
it is just a multiplier, so as reference used "*".

 

[rahul.achates]

plz dont expect work from us ..... if you get stuck or have any issue , you can post here ...we are here to help you.

 

[poornimayn]

I have done 95%.But the problem is ; I'm getting some syntax error in controller which I have designed. Thought I would get some idea as to where I'm going wrong by having a reference!!!..

Anyway thanks for the suggestion!..

Below is the VHDL code for Controller
I get error after end process and end behavior line.
Can anyone please review the code and correct my code.??


entity controller is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
ring_k_1 : in STD_LOGIC_vector(3 downto 0);
b_n : in STD_LOGIC_vector(3 downto 0);
start : in STD_LOGIC;
STOP : out STD_LOGIC;
LOAD_CMD : out STD_LOGIC;
ADD_CMD : out STD_LOGIC;
BYPASS_CMD : out STD_LOGIC);
end controller;

architecture Behavioral of controller is

--declare states
type state_typ is (IDLE, INIT, TEST, ADD, BYPASS);
signal state : state_typ;


begin


process(reset,clk)
--variable i : natural := 0;
variable i : integer range b_n'RIGHT to b_n'LEFT := b_n'RIGHT; -- 3 downto 0 in my program
begin
if reset = '1' then
state <= IDLE;
STOP <= '1';
else if clk'event and clk = '1' then

case state is

when IDLE =>
if START = '1' then
state <= INIT;
-- STOP <= '1';

else
state <= IDLE;
STOP <= '0';
end if;

when INIT =>
LOAD_CMD <= '1';
state <= TEST;

when TEST =>
if ring_k_1(i) = '1' then
state <= IDLE;
STOP <= '1';
elsif ring_k_1(i) = '0' and b_n(i) = '0' then
state <= BYPASS;
BYPASS_CMD <= '1';

-- i := i+1;
if i = b_n'LEFT then
i := 0; -- or use i := b_n'RIGHT;
else
i:= i + 1;
end if;

elsif (ring_k_1(i) = '0' and b_n(i) = '1') then
state <= ADD;
ADD_CMD <= '1';
--i := i+1;

-- i := i+1;
if i = b_n'LEFT then
i := 0; -- or use i := b_n'RIGHT;
else
i:= i + 1;
end if;


end if;


when BYPASS =>
state <= TEST;

when ADD =>
state <= TEST;


end case;

end if; --end for the clock event

end process; --I get error in this line



end Behavioral;--I get error in this line also!!..

 

[rca]

so your issue is how to write a vhdl code, not to write the BZFAD in vhdl.
the case need a default statement.
when you insert a code inside a post, please used the wrap "code".

"when others => NULL;" // do nothing

- - - Updated - - -

please share the error line also.

 

[rahul.achates]

variable i : integer range b_n'RIGHT to b_n'LEFT := b_n'RIGHT; -- 3 downto 0 in my program
begin
if reset = '1' then
state <= IDLE;
STOP <= '1';
else if clk'event and clk = '1' then

in your code , last line should be replaced with
elsif clk'event and clk = '1' then



I have compiled this code , and after including library, it compiled successfully.
put below lines at top of your code --

library ieee;
use ieee.std_logic_1164.all;

Let me know if you still get some error.

Rahul

 

[poornimayn]

variable i : integer range b_n'RIGHT to b_n'LEFT := b_n'RIGHT; -- 3 downto 0 in my program
begin
if reset = '1' then
state <= IDLE;
STOP <= '1';
else if clk'event and clk = '1' then

in your code , last line should be replaced with
elsif clk'event and clk = '1' then



I have compiled this code , and after including library, it compiled successfully.
put below lines at top of your code --

library ieee;
use ieee.std_logic_1164.all;

Let me know if you still get some error.

Rahul

Yes..You are right thats where the error was. I also did the same correction and found its working. Thanks.