[SOLVED] Implementation of an algorithm

[masoud.malekzadeh]

I want to design a processor that one part of which should be like this

W(k)=Pre_W(k)-3*W(k-1)
pre_W(k)=∑x1(i)[x1(i)*W(k-1)+x2(i)*W(k-1)]^3 i=0 to 7

and my arithmetic operations is floating point i should port map them using components .

thanks .

 

[TrickyDicky]

good luck to you. do you have a specific question?

 

[masoud.malekzadeh]

good luck to you. do you have a specific question?

I mean any suggestion how to implement it In Vhdl ?

Thanks

 

[permute]

break this down into a number of operation. then determine the minimum performance required. eg, if you have a 250MHz clock, and need 100k updates, then you have 250000 cycles per update. In such a case, a single FPU might be used along with small BRAMs for instructions/data. If you need 10M updates/second, then you only have 25 cycles. You then need to break the operation up into parallel operations that can be performed by multiple FPU's. In some cases, there will be some common operations and it will make sense to remove the instruction logic and instead use fixed data paths.

one you have a structure in mind, you can start work on a VHDL implementation.

(also, you can investigate alternative representations that might allow fewer multiplications, additions, etc...)

 

[masoud.malekzadeh]

s74:multiplier port map (a =>z1(i),b=>w1(0),clk => clk,result =>pre1(i));
s75:multiplier port map (a =>z2(i),b=>w2(0),clk => clk,result =>pre2(i));
s76:     adder port map (a =>pre1(i),b=>pre2(i),clk => clk,result =>pre3(i));
s77:multiplier port map (a =>pre3(i),b=>pre3(i),clk => clk,result =>pre4(i));
s78:multiplier port map (a =>pre3(i),b=>pre4(i),clk => clk,result =>pre5(i));
s79:multiplier port map (a =>z1(i),b=>pre5(i),clk => clk,result =>pre6(i));
s82:multiplier port map (a =>w1(0),b=>three,clk => clk,result =>nw1(0));
end generate ;

gen13:for i in 0 to 3 generate 
s80:adder port map (a =>pre6(2*i),b=>pre6((2*i)+1),clk => clk,result =>pre7(i));
end generate ;

gen14:for i in 0 to 1 generate 
s81:adder port map (a =>pre7(2*i),b=>pre7((2*i)+1),clk => clk,result =>pre8(i));
end generate ;

--
s83:adder port map (a =>pre8(0),b=>pre8(1),clk => clk,result =>pre9(0));
s84:subtractor port map (a =>pre9(0),b=>nw1(0),clk => clk,result =>w1(1));

In this code i implemented the algorithm that computes only W(1) and the result is ok but to go further W(2),W(3),..... I'm confused ....