s74:multiplier port map (a =>z1(i),b=>w1(0),clk => clk,result =>pre1(i));
s75:multiplier port map (a =>z2(i),b=>w2(0),clk => clk,result =>pre2(i));
s76: adder port map (a =>pre1(i),b=>pre2(i),clk => clk,result =>pre3(i));
s77:multiplier port map (a =>pre3(i),b=>pre3(i),clk => clk,result =>pre4(i));
s78:multiplier port map (a =>pre3(i),b=>pre4(i),clk => clk,result =>pre5(i));
s79:multiplier port map (a =>z1(i),b=>pre5(i),clk => clk,result =>pre6(i));
s82:multiplier port map (a =>w1(0),b=>three,clk => clk,result =>nw1(0));
end generate ;
gen13:for i in 0 to 3 generate
s80:adder port map (a =>pre6(2*i),b=>pre6((2*i)+1),clk => clk,result =>pre7(i));
end generate ;
gen14:for i in 0 to 1 generate
s81:adder port map (a =>pre7(2*i),b=>pre7((2*i)+1),clk => clk,result =>pre8(i));
end generate ;
--
s83:adder port map (a =>pre8(0),b=>pre8(1),clk => clk,result =>pre9(0));
s84:subtractor port map (a =>pre9(0),b=>nw1(0),clk => clk,result =>w1(1));