Hello
I wrote a code in vhdl for a divisor of positive integers (eg 80:7 = 11, remainder = 3). my problem lies in the implementation of this code on FPGA spartan xc3s200 (freq = 50 MHz) to display the result on the 8 LEDs of the FPGA card.
My divider circuit consists of a dividend (7 bits) and a divisor (4 bits), the code will output a quotient (4 bits) and a residue ( 7 bits).
So I'm back on the buttons that control the LEDs the dividend and divisor to see the result of quotient and remainder taking into account the problems of clock generation.
Could you give me some tracks?
Thank you