Zin=R1 ll R2 ll beta*(re+RE)
I think i/p and o/p mean input and output, and that he is talking about a circuit like the one below.
Each gain stage, if used on it's own, would have Zin = 2.5K, Zout = 4.7K, and signal voltage gain = 10.
When they are connected together as shown, Zin of the 2'nd stage is in parallel with Zout of the first stage, so the voltage gain of the first stage is reduced by a factor of 3 (approximately).
Yes, good thinking.Both views are true
But when should be considered as a voltage source in series with the output impedance, or a current source in parallel with the output impedance?Yes, good thinking.
The output of the first stage can be thought of as either a voltage source in series with the output impedance, or a current source in parallel with the output impedance.
But when should be considered as a voltage source in series with the output impedance, or a current source in parallel with the output impedance?Yes, good thinking.
The output of the first stage can be thought of as either a voltage source in series with the output impedance, or a current source in parallel with the output impedance.
But when should be considered as a voltage source in series with the output impedance, or a current source in parallel with the output impedance?Yes, good thinking.
The output of the first stage can be thought of as either a voltage source in series with the output impedance, or a current source in parallel with the output impedance.
Hi Samy... I am just curious to know what you couldn't get from my post #11.
Samy another way to consider your original question, is that since your design is not an ideal voltage source for each stage, you must consider they are serial stages but with parallel loading effects.
That is why I suggested making each stage at least 10x higher Rin vs Rout..., so that I can optimize the gain and consider each stage as a serial stage with minimal parallel loading affects.
Your choice of Base bias resistors makes for very stable bias point at huge expense to AC gain.
Consider let AC Voltage gain = 10
and Impedance gain Rin/Rout =10
Rin2~{R9//R8} // hFE*{R10 // (R7+1/ωC2)}
where // means parallel equiv cct. and hFE =β of Q2 which is usually>>100
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