Hi. Output jitter of each Cyclone FPGA is 500ps. It is not disapperars, it is being accumulated and distorts duty parmeter. But that parameter is very critical for PLL. If you exceed 45...55% duty cycle, PPL will lose a carrier.Acido Cinico said:Dear Kib,
I really cannot understand why this clock jitter
appears only at the n-th board if n is greater
than ten. My system is designed so that each
board receives clock and data and then regenerates
new clock and data signals synchronously.
There should be no jitter at all because they
are n, independent, point-to-point connections.
Do you know if A* Cy* FPGAs have an high PLL
sensitivity to power supply noise? Maybe this
is the cause of my loss of lock.
Regards,
A.C.
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