Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Impedance/Length Matching Tracks in PCB Layout

Not open for further replies.

Engg Electronics

Newbie level 5
Nov 22, 2013
Reaction score
Trophy points
Activity points
Dear All,
Kindly guide me which criteria should follow to do length and impedance matching in PCB layout?
Right now I have a design with different type of flip flops, Do I have to length match of data pins of Flip Flops or just rout them as normal signals?
In addition to my above query at which frequency range do we need to length match in layout?


Technically you need length matching all all frequencies, except for low frequencies the acceptable tolerance is much larger than the PCB size so it's not usually an issue to take into account. So whether you'll have to match the trace lengths only depends on the frequency of your signals.

Matching impedances is done to maximize signal transfer and to avoid reflections from the destination back to the source.

If the delay time on the track length is more than 1/3 to 1/6 of the rise time, then you can expect overshoot from mismatched transmission line impedance and load. The track width to height (w/h) above ground plane dominates complex math for low impedance. so lower h or wider w reduces impedance. CMOS technology determines ESR or RdsOn of drivers, which are typically 50 Ohms to 25 Ohms for ALV type 2.

PECL always uses controlled impedances due to rise time.

Vp = c/√(μ*εr) depending on dielectric Vp= 1/2 to 2/3 *c typ.
where c= 3e8m/s or Vp = 1.5 to 2 e8 [m/s] or 150 to 200 mm/ns

Using a 3x rule of thumb , this reduces ... 50 to 66 mm/ns of rise time.
USing a 6x RUle of thumb, this reduces ... 25 to 33 mm per ns of rise time on your Flip Flop outputs.

The reason for concern on FF is for reasons of lowest latency the outputs are internally fed back, so any transient spikes or ripple may cause false operation and should be buffered, which can be controlled with load and/or transmission line impedances and if not, buffered for external signals that may get crosstalk.

So with slow Rise/fall time, the tolerance on length is wide.

This is from my quick calculations.... not old memories.
SunnySkyguy's answer is good.
I simplified the question.
1. length matching .make sure your setup and hold time margin greater than pcb delay,pcb delay 1ns/6inch.
2.impedance matching .make sure your pcb line impedance and load is the same value.pcb line setup you can use si9000.

You are asking about digital logic PCB. Impedance matching makes only sense if you are using an I/O standard with termination. Is it so?

Length matching is useless unless the basic signal travel time is somehow compensated in the link. Examples

1. DDR2 expects all data bits arriving at the same time because it utilizes a common delay compensation
2. A source synchronous high speed transmission with spearate clock and data. The relation between clock and data has to be maintained

If there are forced timing conditions in logic where you expect data to be stable at the clock edge but somehow latency from unequal logic thresholds or track length delay the clock, it may cause a race condition.

But it's all in the details for worst case timing of the design.

Not open for further replies.

Part and Inventory Search

Welcome to