[SOLVED] I'm stuck,how to port map this...?

[kazvah45]

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Code VHDL - [expand]
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I am working on writing vhdl code for serial multiplier but am stuck on port map. I have uploaded an image for you to see what I am dealing with :
[I]**broken link removed**[/I]
 
Here is my code so far:
[syntax=vhdl]       
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_STD.all;
entity bitserial is
    Port ( A_IN : in  STD_LOGIC_VECTOR (7 downto 0);
           B_IN : in  STD_LOGIC_VECTOR (7 downto 0);
           CLK : in  STD_LOGIC;
           LOAD : in  STD_LOGIC;
           P_OUT : out  STD_LOGIC_VECTOR (15 downto 0);
           DONE : out  STD_LOGIC);
end bitserial;
 
architecture Behavioral of bitserial is
-------I declare some signals-----------
signal weasig :std_logic;
signal wepsig: std_logic;
signal operand1: std_logic_vector(7 downto 0);
signal operand2: std_logic_vector(7 downto 0); 
signal sigP: std_logic;
signal sigA: std_logic_vector(7 downto 0);
 
------Here are my components---------
component FSM is 
Port ( clock1 : in  STD_LOGIC;
           Load : in  STD_LOGIC;
           wr_a : out  STD_LOGIC;
           wr_p : out  STD_LOGIC;
           done : out  STD_LOGIC);
end component;
 
component Reg_A is 
Port ( clock1 : in  STD_LOGIC;
           A_in : in  STD_LOGIC_VECTOR (7 downto 0);
           we_a : in  STD_LOGIC;
           A_out : out  STD_LOGIC_VECTOR (7 downto 0));
end component;
 
component Shift_Reg is 
Port ( clock1 : in  STD_LOGIC;
           B_in : in  STD_LOGIC_VECTOR (7 downto 0);
           we_p : in  STD_LOGIC;
           Sum : in  STD_LOGIC_VECTOR (8 downto 0);
              done : in STD_LOGIC;
           P_out : out  STD_LOGIC_VECTOR (15 downto 0));
end component;
 
component mux2x1 is 
Port ( in0 : in  STD_LOGIC_VECTOR (7 downto 0);
           in1 : in  STD_LOGIC_VECTOR (7 downto 0);
           output : out  STD_LOGIC_VECTOR (7 downto 0);
           sel : in  STD_LOGIC);
end component;
 
 
------Here is where I messed up in the port map------
begin
 
U0: FSM port map(Load => LOAD, clock1 => CLK, wr_a => weasig, wr_p => wepsig, done => );
 
U1: Reg_A port map(clock1 => CLK, A_in => A_IN, we_a => weasig, A_out => sigA);
 
U2: Shift_Reg port map(clock1 => CLK, B_in => B_IN,P_out(15 downto 8) => operand1,
        done => donesig, we_p => wepsig, Sum => );
                       
U3: mux2x1 port map(in1 => sigA, in0 => , sel => sigP , output => operand2);
 
end Behavioral;

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As you can see it is incomplete and there are some unconnected ports because I am confused especially with the operand1 and operand2 signal.
Any replies would be helpful.


Edit: Nevermind I figured it out sorry for disturbing you guys!