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I'm sorry ... for not being able to provide. I am disallowed. And opposes to the new elektroda policy.
The @RM7 i refered to is not just an ISA compatible. My work associate run through my recent posts. I am an @**h0lE to him but worst to my inferiors at work, too. Glad i still have my position on our open processor adaptation.
There shall be an eye on me for a long long time ...
You can still get something relative(...). Which i think is far better than this crap.
For good reason, here follows the file listing. (removed some dumb data files).
accessories.v 6.009 10/08/2000 12:28am A
addr_reg.v 775 07/07/2000 6:42pm A
alu.v 4.803 07/07/2000 9:45pm A
alu_structural.v 15.291 07/07/2000 6:42pm A
arm7.v 3.564 31/08/2000 5:17pm A
arm7_sys.v 1.747 31/08/2000 5:17pm A
armcontroller.v 42.536 10/08/2000 1:43am A
armdatapath.v 8.749 30/08/2000 9:16pm A
AVLMemory.v 4.743 07/07/2000 6:42pm A
barrel.v 4.582 07/07/2000 6:42pm A
booth.v 2.498 07/07/2000 11:46pm A
clock.v 304 07/07/2000 6:42pm A
CPUside.v 26.307 07/07/2000 6:42pm A
defines.v 4.320 07/07/2000 6:42pm A
do_verilog 266 10/07/2000 9:23pm A
exception.mem 190 07/07/2000 6:42pm A
MemoryInterface.v 2.033 07/07/2000 6:42pm A
Memoryside.v 7.337 07/07/2000 6:42pm A
regfile.v 20.662 18/07/2000 12:58am A
shift_maker.v 1.385 07/07/2000 6:42pm A
sign_extend.v 4.131 07/07/2000 6:42pm A
SimpleMemory.v 3.957 10/08/2000 12:47am A
SuperCPSR.v 3.857 07/07/2000 6:42pm A
test_addr_reg.out 650 07/07/2000 6:42pm A
test_alu.out 3.813 07/07/2000 6:42pm A
test_barrel.out 6.168 07/07/2000 6:42pm A
test_booth.out 616 07/07/2000 6:42pm A
test_reg.out 1.129 07/07/2000 6:42pm A
test_regfile.out 6.804 07/07/2000 6:42pm A
test_wd_reg.out 828 07/07/2000 6:42pm A
testbench_addr_reg.v 1.692 07/07/2000 6:42pm A
testbench_alu.v 4.814 07/07/2000 6:42pm A
testbench_arm7.v 10.005 31/08/2000 5:23pm A
testbench_AVLMemory.v 3.885 07/07/2000 6:42pm A
testbench_barrel.v 3.587 07/07/2000 6:42pm A
testbench_booth.v 4.827 07/07/2000 6:42pm A
testbench_controller.v 8.731 07/07/2000 6:42pm A
testbench_CPUside.v 7.107 07/07/2000 6:42pm A
testbench_dedsec.v 10.363 07/07/2000 6:42pm A
testbench_memory.v 2.982 07/07/2000 6:42pm A
testbench_regfile.v 4.249 07/07/2000 6:42pm A
testbench_regfile2.v 4.356 07/07/2000 6:42pm A
testbench_regfile3.v 4.544 07/07/2000 6:42pm A
testbench_regfile4.v 4.587 07/07/2000 6:42pm A
testbench_SimpleMemory.v 3.704 07/07/2000 6:42pm A
testbench_wd_reg.v 1.758 07/07/2000 6:42pm A
wd_reg.v 573 07/07/2000 6:42pm A
59 files; 273.571 bytes
Total: 59 files; 273.571 bytes
If i am misbehaving i will totally remove my post.
I DON'T HAVE THE @RM CORE... my supervisor at work has changed my position, literally speaking. I don't have access to any hard disk with the @RM core. Not any more. I only have the file listing which i extracted 15 days ago.
Let's talk about t00l knowledge instead, or open designs. For my work i use freeware tools (e.g. some Linux builds, VHDLSimili etc).
Do you people want to create an ARM ISA compatible? Why not start from the ARM ARM and it should be 3 man-weeks for the behavioral model.
At least this is what i do is similar occasions (FFT datapaths, DLX, vector processing library, scalar adder and multiplier library, XYZ multimedia core etc). Do the actual coding myself. It is more fun!!!
I agree with penetrator, we better turn our energy to some other open designs other than ARM, as ARM is very protective for their IP so the open community has even little chance to work with an ARM clone, such as nnARM.
I remember I got an ARM clone from CMU before, but don't know if it is still available.
If your purpose is learning, why not come to LEON or OpenRISC? I am playing happily with them and they are really nice compared to the previous ARM clone I did access to.