Thanks a lot for the reply, a lot of things have been cleared up:razz:
I may have a 2nd thought about my selection of filters, but either way I wanna complete this question first. Could you help me with a few points that I dont understand in your answer?
About the filter implementation in the FPGA:
First, do not implement the direct form of the 5th order directly, you should implement it using biquads - i.e. as a cascade connection of one and second order filters. Check **broken link removed** for the Matlab function tf2sos, which will give you the coeff. values you need, and some good advice too.
So you mean that I should implement the IIR filter by multiplying together sections of “transfer functions" (as Π(Xi(z)/Yi(z))) with SOS and G? so in difference equation it should be something like y[n]=Σb0i*w[n-i], w[n]=x[n]+Σa0i*w[n-i]? but what if I have three sections?
About the wordlenght: There are different ways to estimate an appropriate wordlenght for your filter, just google about filter scaling. For the coeff. wordlenght, you do not need 18 bits, you can have less bits, check 8 bits. BUT, your data path should be greater, maybe 16bits - again, check scaling!
I'm checking filter scaling in google, haven't found any tutorial etc for beginners. will keep looking...
but suppose my ADC is 16bit, thus my input signal is 16bit width. Then if my coefficient is 8th. How should I transform the coefficient into 8bit word? for example, -1.034, should I do coeff= {1'b1,round(1.304*2^7)=167} which doesn't make sense since 167 >2^7. or coeff={1'b1, 1'b1, round(0.304*(2^5))=10=01010}, the 8bit word is 1bit for sign, 2bit for integer and 5bit for fractions.
If I were you, I will start by designing everything with a fixed wordlenght of 24 bits (use generics to easy changes latter) - which will be 8 bits for coeff. + 16 bits of datapath. For truncating the data (i.e. after multiplication or output) you should take care about which bits you need to remove, it is not only the MSB but also some of the LSB too. Keep in mind, that if you have two numbers aa.bb * cc.dd = eeee.ffff (where the values after the . are the fractions) you should keep ee.ff
Usually you need a higher wordlenght inside your filter instead of the ADC/DAC bits is because internally the filter would need more space to store results and avoid overflow and limit noise.
The truncation thing helps a lot! But one more question, if my DAC is 12bit, and I have 8bit coeff (2.5) times 16bit input (6.10), the result will be 24bit, and is it (2+6.5+10)? then how should I decide which bits to keep?
sorry if my questions dont make sense or I didnt make them clear enough... is there some sorta of tutorial for beginners about questions like that? I am interested in the theory too:smile:
---------- Post added at 14:34 ---------- Previous post was at 14:27 ----------
Thanks for replying!! kalyanasv.
the piece of code I got online is as below:
module sine_cos(clk, reset, en, sine, cos);
input clk, reset, en;
output [13:0] sine,cos;
reg [13:0] sine_r, cos_r;
assign sine = sine_r + {cos_r[13], cos_r[13], cos_r[13], cos_r[13:3]}; //devide by 8, or sample the period by 8
assign cos = cos_r - {sine[13], sine[13], sine[13], sine[13:3]};
always@(posedge clk or negedge reset)
begin
if (!reset) begin
sine_r <= 0;
cos_r <= 120;
end else begin
if (en) begin
sine_r <= sine;
cos_r <= cos;
end
end
end
endmodule // sine_cos
what do you mean by 'corresponding bits'? the ADC bits?
For filtering, I may use a FIR filter instead, but I wanna finish this and understand the implementation for IIR first =)
I am not following what you said about convolution sum for which i need a loop and generate all sums... it's like what we do in matlab, but how can I do that in fpga? could you be more specific?