#### allison_www

##### Newbie level 4

I am trying to implement a lock-in amplifier in FPGA. To do tat, I used ALTPLL to generate a locked clock, clk_lock, then I found a piece of Verilog code online to transform the clk_lock into a 14-bit sine wave, which is my reference signal (not sure if it's ok to do it that way...). Then I used a multiplier to mixer my input signal (14-bit) with the reference signal.

Next I want to implement a filter to keep only the DC part. I checked up online and it seemed to me that an IIR filter was better since it's more energy efficient. I generated the specs (154Khz sampling rate, 5khz passband, 8khz stopband) of the filter in matlab fdatool. It's a 5 order iir filter. the coefficients of the transfer function are:

b=[0.00185 -0.00505 0.00323 0.00323 -0.00505 0.00185]

a=[1 -4.76 9.10 -8.77 4.25 -0.828]

I read some material online and find that what I'm supposed to do is to multiply all coefficients by 2^14 and round them as fixed-points values if I want 14-bit coefficients. The problem is, after multiplication, some coeff are bigger than 2^13(the 1st bit is sign), thus I have to broad the bit width of coefficients to 18-bit. I add 4 bit 0000 to the left of the input signal so it is 18bit too.

Then I should write the difference equation as y[n]=b0*x[n-1]...+a0*y[n-1], where I can use registers to store y[n-1],y[n-2]...x[n-1], x[n-2]...and the multiplication should be 36-bit since both input signal and ref signal are 18-bit width. Then I probably should cut the right most 18bit data off so my result is 18bit width...but that doesn't make sense since I may want 14bit signal...i dont know.

SO, could any1 pls tell me if I am on the right track/what is the right way/where I can find the right way to solve the problem? I looked up a lot of information online but still got confused. I am new to FPGA and all I have done before is based on matlab. Thank you!!