it should be
Code VHDL - [expand] |
1
| process (digit) begin |
also you have a width problem with the following line as your assigning a 8-bit wide value to a 9-bit value.
Code VHDL - [expand] |
1
| sumwithcarry <= "00000000" + datapac1 + datapac2 + datapac3 + datapac4 + datapac5 + datapac6; |
I also you shouldn't be assigning sumwithcarry outside the process that is assigning it too.
Others more familiar with VHDL will also probably chime in that you shouldn't be using std_logic_arith (synopsys extension) as it's been deprecated. There are IEEE packages which support addition using other types.
regards