[SOLVED] If FPGA Resource is more than 90%...

[sureshaa]

Hi all,

I am using Spartan 3A device. After full design I have added chip scope. My resource utilization is 98% with CDC( 83% without CDC). I didn’t get any constraint error. My max freq also met with my requirement. But I notice one different behavior.
When I add CDC file in my project, my output assignment operation is not working, even though all input conditions are met.

If I remove the CDC file from my project, my out assignment operation is working, when input conditions are met. Please let me know if the resource utilization is more, whether the FPGA will behave like this?

 

[FvM]

Re: If Resources is more than 90%

The observation suggests that your design involves timing problems which are not covered by the existing constraints.

 

[ads-ee]

That shouldn't happen under normal circumstances. I would suggest checking the following things.

1) verify you don't have any unconstrained paths in the design. Adding chipscope with that amount of utilization increase will affect timing.
2) if you have logic optimization turned on, turn it off, there is a bug in optimization that can result in the design becoming corrupted (this was per factory recommendation).

Regards