Apr 23, 2014 #1 S sun_ray Advanced Member level 3 Joined Oct 3, 2011 Messages 772 Helped 5 Reputation 10 Reaction score 5 Trophy points 1,298 Activity points 6,828 Are these following events allowed in if-else in Verilog? If not please provide the reason. If (posedge clk) q<= d; Regards
Are these following events allowed in if-else in Verilog? If not please provide the reason. If (posedge clk) q<= d; Regards
Apr 24, 2014 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,501 Helped 14,757 Reputation 29,796 Reaction score 14,124 Trophy points 1,393 Location Bochum, Germany Activity points 298,438 Short answer quoted from IEEE 1800-2012: (...) an edge can trigger a flip-flop, but the state of the edge cannot be ascertained, i.e., if (posedge clock) is illegal. Click to expand...
Short answer quoted from IEEE 1800-2012: (...) an edge can trigger a flip-flop, but the state of the edge cannot be ascertained, i.e., if (posedge clock) is illegal. Click to expand...
Apr 24, 2014 #3 R rahul.achates Banned Joined Nov 19, 2009 Messages 150 Helped 25 Reputation 120 Reaction score 56 Trophy points 1,308 Location Bangalore Activity points 0 well said