if else use in Verilog and event, provide reason

[sun_ray]

Are these following events allowed in if-else
in Verilog? If not please provide the reason.


If (posedge clk)
q<= d;

Regards

 

[FvM]

Short answer quoted from IEEE 1800-2012:

(...) an edge can trigger a flip-flop, but the state of the edge cannot be
ascertained, i.e., if (posedge clock) is illegal.

 

[rahul.achates]

well said