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IF ELSE Syntax error for Block RAM

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kenjo

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Hello,

I am a bit new to VHDL and am currently trying to write VHDL code to write to a block RAM. I am getting a syntax error "near else" and "near If". I have been trying to figure out what this could mean for quite some time and cannot seem to find a solution. I am guessing it may be something trivial that I am missing but I am not sure. I have listed my code below. Any assistance is appreciated, thanks.




Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
 
entity top_level is
    Port ( clk_100MHz : in  STD_LOGIC; -- FPGA's external oscillator
           switch : in  STD_LOGIC; -- hooked to slide switch SW(0) on Atlys board
              RESET: in STD_Logic;
           leds : out  STD_LOGIC_VECTOR (7 downto 0)); -- drives all eight LEDs on board
end top_level;
 
architecture Structural of top_level is
 
component ck_divider
    Port (CK_IN : in STD_LOGIC;
            CK_OUT : out STD_LOGIC);
end component;
 
 
component rom8x8
    PORT (addr : in  std_logic_vector(2 downto 0);
            dout : out std_logic_vector(7 downto 0));
end component;
 
-- This component is created using the Core Generator. Its VHDL description
-- is inside ipcore_dir/my_bram8x8.vhd, which was created during the use
-- Core Generator as explained in the lab.
component my_bram8x8
  PORT (
    clka : IN STD_LOGIC;
    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    addra : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
end component;
 
signal clk_1Hz : STD_LOGIC;
signal my_addr_counter : STD_LOGIC_VECTOR (2 downto 0) := "000";
signal dout_rom8x8, dout_bram8x8 : STD_LOGIC_VECTOR (7 downto 0);
signal dina_null : STD_LOGIC_VECTOR (7 downto 0);
signal data_input : STD_Logic_Vector (7 downto 0);
signal wea_null : STD_LOGIC_Vector (0 downto 0); 
 
begin
 
 
clock_divider : ck_divider port map (clk_100MHz, clk_1Hz); -- poor instantiation
memory1 : rom8x8 port map (addr => my_addr_counter, dout => dout_rom8x8); -- better instantiation
-- Instantiate BRAM.
memory2 : my_bram8x8 port map (
    clka => clk_1Hz, -- clock for writing data to RAM
    wea => wea_null, -- write enable signal for Port A
    addra => my_addr_counter, -- 3 bit address for the RAM
    dina => dina_null, -- 8 bit data input to the RAM
    douta => dout_bram8x8); --8 bit data output to the RAM
 
 
-- select between ROM display and BRAM display
multiplex_out : process (clk_1Hz) is
begin
    if (clk_1Hz'event and clk_1Hz = '1') then
        case switch is
            when '0' =>
                leds <= dout_rom8x8; -- Output display of ROM data
            when '1' =>
                leds <= dout_bram8x8; -- output display of BRAM data
            when others => NULL; 
        end case;
        my_addr_counter <= std_logic_vector( unsigned(my_addr_counter) + 1); -- cycles through the address. Initialized to 000
    end if;
end process;
 
 
 
-- Pseudo code for Write BRAM
 
-- Begin Process (Trigger on rising edge of clock)
 
-- IF rising_edge of CLK then:
--  IF RESET button is pushed THEN set current address data to "0"
--  else if write_enable is pushed then prompt for data input
--      WHEN specified adress is selected THEN write switch configuration to data_in
--  output data_in
-- end if's
-- end process
 
-- write to BRAM
write_bram : process (clk_1Hz, RESET, wea_null) is
begin
    if (clk_1Hz'event and clk_1Hz = '1') then
        if  RESET = '1' then dout_bram8x8 <= "00000000"
        else if (wea_null = '1') then
        -- statements to write input to selected or current adress
 
            if my_addr_counter = "000" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "001" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "010" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "011" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "100" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "101" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "110" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "111" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            end if;
        end if;
        end if;
    end if;
end process; 
        
 
end Structural;

 
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kenjo

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Thanks. I made some changes to the code and now I get this error at the beginning of the first elsif statement: Found '0' definitions of operator "=", cannot determine exact overloaded matching definition for "="
I am not sure what this means. Is it another syntax error? Or should I try and restate this in a different way?


Code VHDL - [expand]
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write_bram : process (clk_1Hz, RESET, wea_null) is
begin
    if (clk_1Hz'event and clk_1Hz = '1') then
        if  RESET = '1' then 
            data_input <= "00000000";
            dina_null <= data_input;
            dout_bram8x8 <= dina_null;
        elsif (wea_null = '1') then
        -- statements to write input to selected or current adress
 
            if my_addr_counter = "000" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "001" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "010" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "011" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "100" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "101" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "110" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            elsif my_addr_counter = "111" then 
                dina_null <= data_input;
                dout_bram8x8 <= dina_null;
            end if;
        end if;
    end if;
end process;

 
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vGoodtimes

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signal wea_null : STD_LOGIC_Vector (0 downto 0);
'0' is a std_logic, "0" is a 1 bit std_logic_vector.
 

TrickyDicky

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You should not be using a clock divider. You can get ask sorted of problems with logic generated clocks. You should generate a clock enable instead and clock all logic at the 100mhz clock rate
 

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