I am using an if else block inside an always @(clock) block. My question is, the if statement is governed by a select and my sensitivity list does not contain this signal as its driven by clock and reset.
Is this a correct representation of the code:
Code:
always @(posedge CLK or negedge RST) begin
if (!RST) shift_reg <= input_data;
else
begin
if (data_sel == 2'b11)
begin
if (flag) shift_reg <= shift_reg;
else shift_reg <= "do something else (some logic)";
end
else shift_reg <= shift_reg;
end
The inside if statement is governed by data_sel which is not in the sensitivity list. Is this wrong or is there some other way to implement this logic?
Sensitivity list entries are neither required nor allowed for the synchronous (CLK edge sensitive) part of the always statement.
The "shift_reg <= shift_reg" statements are however useless and can be omitted. All registers are keeping there previous value unless assigned a new one.
Sensitivity list entries are neither required nor allowed for the synchronous (CLK edge sensitive) part of the always statement.
The "shift_reg <= shift_reg" statements are however useless and can be omitted. All registers are keeping there previous value unless assigned a new one.
I understand. This works as there are only 2 cases. But if i have more than two cases, I will have to use "CASE" which requires its own always block like