Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

if ( ~|counter) in verilog

Status
Not open for further replies.
S

sivaram248

Newbie level 2
Joined
Jan 23, 2014
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
10
please tell me here what is the operation is going on in verilog?

if ( ~|counter)

Thank you
sivaram
 

An unitary NOR reduction operator. Review IEEE 1800, clause 11.4.9 Reduction operators

Possibly more familiar: if (counter == 0)
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top