lxcpku
Junior Member level 3

ie.verimix
Hi,all :
i met an error below when i run mix-signal simulation and do not know how to solve it, anyone knows about that and gives me some advice ? thanks a lot
it looks like variable Namelength is too long to place in a line. however , the simulator could not recognize that
Error! syntax error [Verilog]
"IE.verimix", 34: pucore<-
1 error
"I0/u_asicbody/U12/99999"); // /I0/u_asicbody/U12/net11
$vmx_define_import(
test.top.I0.u_asicbody.u_sc100top.u_SC100.u_sc100_top.u_sc100_mpu.u_sc100_m
pucore.U676.mixedNet99999,
"I0/u_asicbody/u_sc100top/u_SC100/u_sc100_top/u_sc100_mpu/u_sc100_mpucore/U
676/99999"); //
Hi,all :
i met an error below when i run mix-signal simulation and do not know how to solve it, anyone knows about that and gives me some advice ? thanks a lot
it looks like variable Namelength is too long to place in a line. however , the simulator could not recognize that
Error! syntax error [Verilog]
"IE.verimix", 34: pucore<-
1 error
"I0/u_asicbody/U12/99999"); // /I0/u_asicbody/U12/net11
$vmx_define_import(
test.top.I0.u_asicbody.u_sc100top.u_SC100.u_sc100_top.u_sc100_mpu.u_sc100_m
pucore.U676.mixedNet99999,
"I0/u_asicbody/u_sc100top/u_SC100/u_sc100_top/u_sc100_mpu/u_sc100_mpucore/U
676/99999"); //