IC layout parasitics extractor

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cretu

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Hi all,

i need some advice/suggestions regarding ic layout parasitics extractors. ineed for a high-speed design to simulate with extracted layout parasitics.I used in the past RF_columb*s with cadence. Can u suggest something better? do you know if columbus is the best tool? thanks in advance for you replies/suggestions
 

For analog circuits, IC Extract is a decent tool. Make sure you check the option for extracting capacitors between nodes and NOT to ground.



colombo2
 

For analog circuits, IC Extract from Cadence is a decent tool. Make sure you check the option for extracting capacitors between nodes and NOT to ground.



colombo2
 

Hello,
Since you are using C@dence, try Dr@cula, Div@, Assur@ as well.
However if you are doing RF design, it would not be a good choice.
Plus, so far the process migrate to deep submircon, most foundries did not support C@dence Dr@cula any more, but Ment0r C@libre/xC@ilbre did...

Regards,
 

Hi,

thnaks for your input..I knew partially the industry trend...I am more interested in getting the feeling if Columbus is good enough and if I can get it for linux.
 

As I known, there is no 0.35um Tech file(T*MC) available for C0lumbus...
I agree C0lumbus has a pretty good feature rather than xC@libre does.
But currently, it seems xC@libre did the most work in this field.
C0lumbus needs users to evaluate and endorse...

Regards,
 

hi Ryan,

you are right. I know that when using co*lumbus in the past the results we got from post layout sims was closer to reality. The R,L,C extraction is worth it, especially for High speed designs(over 10GB/s)
 

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