IC Compiler (SYNOPSYS) HELP!!! i

[chimera086]

Hi everyone... i really need help...

i run the ic compiler gui already using icc_shell -gui and have my setup done using the gui also... my search path, link library and target library are setup already and the same is done with my TLU+ files... i have created a Milkyway library as well, with the technology file and the input reference libraries. but the problem comes when i want to import my verilog file....the error goes like below....

Error: Module 'DFFARX1' is not defined. (MWNL-297)
Error: Verilog parser cannot parse the /RISCforICC/icc/source/RISC_SPM_gate2.v source file. (MWNL-047)
No such file or directory
Error: Current design is not defined. (UID-4)

I have read forums here but it didnt answer my question.... they say that maybe i just missed linking my reference library but i have done it already... and i have look into the first error that i have and it seem not consistent... i looked into the reference library and found DFFARX1 but in the FRAM its DFFARX1_1... i just dont have any idea about this..... hope that you can help me guys...... thank you....

 

[sharankumargoud]

Hi Chimera, Can you please tell me that are you giving verilog file or technology mapped netlist file?

 

[cherizkrish]

Hey hi,

Even I face the same issue.. I guess you need to import files again from gui. File > import..

 

[chimera086]

Hi sharankumargoud,

During the synthesis of my verilog file using DC compiler, it created the files .DDC, .SDF, .SDC and .V. The .V file is the one i have imported in the ICCompiler after i have created my MW library....

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Hi Sharankumargoud,

during the synthesis of my verilog file using the Design compiler, it created the files .DDC, .SDC, .SDF and .V. The .V file is the one which i have imported in the ICCompiler after i have created the MW library...

BTW, thanks for the reply...

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Hi cherizkrish

i have done that already and the error just keep on repeating.... i just dont know what to do... i guess the problem is in the synthesis part... but there was no error generated during the design process of the Design compiler.... they say maybe the problem is on the links or paths of the files that i have... but i have checked it already......

BTW thanks for the reply....

 

[sharankumargoud]

Check these.
- Are the target library and reference file are of same type? I mean , they are of same PDK
-Check the top cell name while creating the MW
-Check the setup as remedy
Hope its helps u