Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

IC Compiler : mapping pin (gnd <-> vss) for Synthesis & Physical implementation

Status
Not open for further replies.

pierre13

Junior Member level 3
Junior Member level 3
Joined
Aug 9, 2012
Messages
27
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,725
IC Compiler : mapping pin (gnd <-> vss) for Synthesis & Physical implementation

Hello !!

I have some std cells with the following pins : vdd, vnw, vss, vpw. FRAM views .lib
Then, I have some other cells with the following pins : vdd, vdds, gnd, gnds. FRAM views and .lib

I would like to make the synthesis and the P&R with ICC version :
G-2012.06-SP4/bin/icc_shell

Is it possible to use a mapping file ? or do I have to make all the cells pins definition consistent ?

Something like :
vdds = vnw
gnd = vss
gnds = vpw


Thanks a lot !!
P.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top